Showing posts with label ARM microprocessors. Show all posts
Packet.net strong-ARMs cloud for $0.005 per core per hour
CEO
Zachary Smith told The Register that the company's cooked up the cloud for a
few reasons. Price is one: Packet will offer ARM cores at a tenth of the price
it charges for Intel cores, at US$0.50 per hour per server, or $0.005 per core
per hour. Smith thinks that will be a head-turner by itself.
Packet.net,
a bare-metal cloud aimed at developers, has flicked the switch on cloud-running
servers powered by a pair of Cavium's 48-core ARMv8-A ThunderX processors.
He
also thinks developers will appreciate the chance to try native Docker on
many-cored machines and appreciate the opportunity an ARM-powered cloud
represents as they pursue 100 per cent portable software. He believes open
source folk will see the arrival of an ARM-powered cloud as incentive to
accelerate cross-platform versions of their pet projects.
Even
ARM will benefit, he says, because having a working cloud on the market will
give both it and licensees more reason to innovate for the data centre.
ARM's
recent purchaser, SoftBank, recently tipped some money into Packet.net, but Smith
swears he's had a long-term ambition to offer an ARM-powered cloud, if only
because he enjoys having multiple ARM server CPU vendors willing to do deals.
That kind of competition is not currently possible in the x86 world, at least
until AMD returns to servers in 2017.
Smith
also feels that ARM clouds are inevitable, probably thanks to telcos looking to
offer cores to rent at the edge of their networks. The CEO feels that telcos
will build edge clouds because they're sick of over-the-top players having all
the fun and profits: this time telcos want to build a revenue-generating
platform beyond mere carriage.
For
now, Packet's ARM cloud offers 64-bit Ubuntu 16.04, but promises that CoreOS,
FreeBSD and CentOS are in the pipeline. Four different ARM server
configurations are also in the works.
The
cloud will have an API, a portal, and will also be accessible from DevOps
favourites likes Terraform and Ansible. Four of the company's bit barns – in
Parsippany New Jersey, Sunnyvale California, Amsterdam and Tokyo – will offer
the service as of Tuesday.
"We
want to offer a super-cheap, 'you would be stupid not to try it'
offering," Smith told The Register. "If we can get the open source
ecosystem rebooted, I think Intel's grip on the data centre will be
shattered." ®
Nobody tell Linux, okay?
Intel's followed up on its acquisition of Altera by baking a microprocessor into a field-programmable gate array (FPGA).
Intel's followed up on its acquisition of Altera by baking a microprocessor into a field-programmable gate array (FPGA).
The Stratix 10 family is part of the
company's push beyond its stagnating PC-and-servers homeland into emerging
markets like high-performance computing and software-defined networking.
Intel says the quad-core 64-bit ARM Cortex-A53
processor helps position the device for “high-end compute and data-intensive
applications ranging from data centres, network infrastructure, cloud
computing, and radar and imaging systems.”
Compared to the Stratix V, Altera's
current generation before the Chipzilla slurp, Intel says the Stratix 10 has
five times the density and twice the performance; 70 per cent lower power
consumption at equivalent performance; 10 Tflops (single precision); and 1 TBps
memory bandwidth.
The devices will be pitched at
acceleration and high-performance networking kit.
The Stratix 10 “Hyperflex architecture”
uses bypassable registers – yes, they're called “Hyper-Registers”, which are
associated with individual routing segments in the chip, and are available at
the inputs of “all functional blocks” like adaptive logic modules (ALMs),
embedded memory blocks, and digital signal processing (DSP) blocks.
Designs can bypass individual Hyper-Registers,
so design tools can automatically choose the best register location. Intel says
this means “performance tuning does not require additional ALM resources … and
does not require additional changes or added complexity to the design's
place-and-route.”
The company reckons the design also
cuts down on on-chip routing congestion.
There's more on the architecture in
this white paper.
Oh, and it's got an on-chip ARM core.
Did we mention that? ®
The Cortex-R52 by ARM was designed to address functional safety in systems that need to comply with ISO 26262 (ASIL D) and IEC 61508 (SIL 3). ST Microelectronics is the first chip vendor, which licensed the processor.
ARM processor dedicated for functional safety applications
ARM processor dedicated for functional safety applications
The
Cortex-R52 offers hardware-enforced separation of software tasks to ensure that
safety-critical code is fully isolated. This allows the hardware to be managed
by a software hypervisor policing the execution and resourcing of tasks. By
enabling the precise and robust separation of software, the Cortex-R52
decreases the amount of code that must be safety-certified, so speeding up
development as software integration, maintenance and validation is easier. The
processor also deals with increased software complexity while delivering the
determinism and fast context switching that real-time systems demand. The
safety processor implements hardware to simplify the integration of
increasingly complex real-time software environments while providing the robust
separation of software necessary to protect safety-critical code. It introduces
an extra privilege level, which provides support for a hypervisor. This is all
achieved without impacting the determinism needed for real time systems and
while providing higher levels of performance from single and multicore
configurations.
"The
Cortex-R52 is the first processor built on the ARMv8-R architecture and it was
designed from the ground up to address functional safety," said James
McNiven from ARM (United Kingdom). "We are helping partners to meet
particular market opportunities, especially in fully autonomous vehicles and
robotics systems where specific functionality is required for safety-critical
tasks. By documenting the strict development process, fault modeling and
supporting software isolation, ARM is enabling a faster route to market for
partners addressing these applications."
The
British company, which was recently acquired by Softbank (Japan) for about 31
billion US-$, presented also the first customer for the new processor: ST
Microelectronics. It is expected that French-Italian chipmaker will provide
models featuring CAN connectivity – of course, supporting the CAN FD protocol.
"The Cortex-R52 supports our Smart Driving vision by enabling a new range
of high-performance, power-efficient SoCs for any in-vehicle application
demanding real-time operation and the highest levels of functional safety,
including powertrain, chassis and ADAS," said Fabio Marchiò from ST
Microelectronics. "The Cortex-R52's ability to compartmentalize software
provides our users with the best solution for safety without loss of
determinism. Its virtualization support simplifies the consolidation of
applications and functions into a single processor, delivering a shorter
integration time." First micro-controllers based on Cortex-R52 are
expected on the market by 2018.
As
an ECU manufacturer, Denso (Japan) supports the launch of the safety processor:
"We welcome the development of new processor technology to drive the
evolution of embedded real-time control, which is critical to advancing
capabilities for autonomous systems," said Hideki Sugimoto. The
availability of ARM’s Fast Models and Cycle Models enables software partners to
develop solutions for the processor. They further speed the path to market as
software developers will get access to the Cortex-R52 early in the design
process. The Cortex-R52 offers a 35-percent performance uplift compared to the
Cortex-R5, which is already deployed in a range of safety applications. It has
achieved a score of 1,36 Automark/MHz on the EEMBC AutoBench using the Green
Hills Compiler 2017.
"Green
Hills Software is expanding its support for ARM processors with optimizing
compiler solutions for the Cortex-R52," said Dan Mender. "Through
close collaboration with ARM, we deliver the industry's highest performing
safety certified compiler for the Cortex-R52, enabling customers to develop
safety-critical products at the highest certified levels of automotive (ASIL D)
and industrial safety (SIL 3)."
