Showing posts with label ARM announcement. Show all posts
A sprinkling of Internet of Things ... and ... it's alive: Startup
Igneous Systems has re-discovered and re-imagined the idea of customers renting
an externally managed system on their premises, giving it an Internet of Things
(IoT) and public cloud make-over.
Customers
start with a 2x1 system of two dataRouters and one dataBox at a usable capacity
of 212TB. The dataRouters and dataBoxes can scale independently.
The
new angles are that IoT devices can generate vast amounts of data which is
difficult to send to a set of on-premises servers or the public cloud because
transmission is too slow and/or the data is sensitive and needs to be retained
on site.
Igneous's
answer is to store it locally in a public cloud-like, scale-out,
hyper-converged system that can run some compute processes on the data, and be
managed through the cloud. Example compute workloads are auto-tagging, metadata
extraction, image processing, and text analysis.
Igneous
owns and operates the on-premises equipment and the customer has a
capacity-based subscription pricing scheme. The systems are remotely managed
and monitored through a cloud service, and there is automated cloud management
processes for upgrades, troubleshooting, and failure management. Igneous claims
that these functions can be performed on a mirror of incoming and outgoing data
streams without slowing down low-level system functions.
The
Igneous architecture utilises a microservices approach and incorporates stream
processing, an event-driven framework, and container services.
The
equipment is based on ARM-powered nano-servers, with each being a disk drive,
ARM processor and Ethernet link. Igneous calls this a JBOND - Just a Bunch of
Networked Drives. There is a SoC (System On Chip) with a Linux-running Marvell
32-bit Armada 370 processor, with two Cortex-A9 cores running at up to 1 GHz.
Networking is via two 1 GbitE ports, and the nanoservers operate in a kind of
mesh.
It
reminds El Reg of Seagate's Ethernet-addressed Kinetic disk drives, except that
Igneous has had its own nanoservers built and the JBOND is accessed as an S3
data store. Any processing capabilities to operate on the stored data need
adding. Data is stored using erasure coding and failed nanoserver disks have
data rebuilt using other nanoservers.
We
also think 32-bit ARM CPUs look a bit light in compute power terms and 64-bit
ones will need to be used if any serious compute is going to be done on the
data.
Access
is via Amazon's S3 API across a customer's 10Gbit Ethernet infrastructure.
Other public cloud service access protocols will probably be added in the
future.
A
dataBox has 60 drives (nano-servers with 6TB disks) in a 4U enclosure and is a
capacity store. A dataRouter is a stateless 1U server used for protocol
endpoints and keeping track of data in the nanoserver mesh.
There
is some existing third-party software support. For example, Commvault Virtual
Server Protection (VSP) enables users to back up to an Igneous System and
Infinite IO works with Igneous.
This
Igneous nanoserver kit is an interesting start in what we might ultimately call
micro or nano hyper-converged systems. Getting involved with it means
leading/bleeding edge work for Linux and S3 buffs.
Get
a datasheet here. The Igneous Data Service is available immediately to
customers in North America. Customers can purchase annual subscriptions in
increments of 212TB of usable capacity, starting at under $40,000 (equivalent
to 1.5 cents/GB/month). This is claimed to be lower than the cost of S3 (3
cents/GB/month). Volume discounts are available, based on installed capacity or
contract duration. ®
CHIPMAKER Intel's Altera unit has unveiled the Stratix 10, a quad-core FPGA that features a 64-bit ARM Cortex-A53 with five times the density and twice the performance of Altera's previous generation Stratix V.
The Stratix 10 offers
70 per cent lower power consumption for the same performance and will be
produced on Intel's latest 14nm process technology.
The
device was unveiled by Dan McNamara, corporate vice president and general
manager of the Programmable Solutions Group (PSG) at Intel.
"Stratix
10 combines the benefits of Intel's 14nm tri-gate process technology with a
revolutionary new architecture called HyperFlex to uniquely meet the
performance demands of high-end compute and data-intensive applications ranging
from data centres, network infrastructure, cloud computing and radar and
imaging systems," he said.
The
device is intended for data centre applications and networking infrastructure,
and comes after Intel signed adeal in August with ARM to produce chips based on ARM's
intellectual property in Intel's most advanced chip production facilities.
The
arrangement came after Intel struck a deal in2013 to make 64-bit ARM chips for Altera when it was
designing the Stratix 10.
"FPGAs
are used in the data centre to accelerate the performance of large-scale data
systems. When used as a high-performance, multi-function accelerator in the
data centre, Stratix 10 FPGAs are capable of performing the acceleration and
high-performance networking capabilities," explained McNamara.
The
device is among the first new products that Intel will produce on its own fabs
that incorporate ARM microprocessor technology since offloading the Xscale
business to Marvell in 2006.
Intel
had acquired the Xscale business, then called StrongARM, after buying Digital
Equipment's semiconductor operations in the late 1990s.
Meanwhile,
Intel completed the acquisition ofAltera in December 2015, when CEO BrianKrzanich said: "We will apply Moore's Law to grow today's
FPGA business, and we'll invent new products that make amazing experiences of
the future possible - experiences like autonomous driving and machine
learning."
This
is not the first time that a chip design company has blended memory with
switching fabric. The Xilinx Zynq-7000 is an all-programmable SoC comprising
two 32-bit ARM Cortex-A9 cores, an FPGA and a number of controller cores to
handle Ethernet, USB and other controllers.
Intel-owned
Altera has produced a white paper explaining the technicalintricacies of the Stratix 10. ยต
Nobody tell Linux, okay?
Intel's followed up on its acquisition of Altera by baking a microprocessor into a field-programmable gate array (FPGA).
Intel's followed up on its acquisition of Altera by baking a microprocessor into a field-programmable gate array (FPGA).
The Stratix 10 family is part of the
company's push beyond its stagnating PC-and-servers homeland into emerging
markets like high-performance computing and software-defined networking.
Intel says the quad-core 64-bit ARM Cortex-A53
processor helps position the device for “high-end compute and data-intensive
applications ranging from data centres, network infrastructure, cloud
computing, and radar and imaging systems.”
Compared to the Stratix V, Altera's
current generation before the Chipzilla slurp, Intel says the Stratix 10 has
five times the density and twice the performance; 70 per cent lower power
consumption at equivalent performance; 10 Tflops (single precision); and 1 TBps
memory bandwidth.
The devices will be pitched at
acceleration and high-performance networking kit.
The Stratix 10 “Hyperflex architecture”
uses bypassable registers – yes, they're called “Hyper-Registers”, which are
associated with individual routing segments in the chip, and are available at
the inputs of “all functional blocks” like adaptive logic modules (ALMs),
embedded memory blocks, and digital signal processing (DSP) blocks.
Designs can bypass individual Hyper-Registers,
so design tools can automatically choose the best register location. Intel says
this means “performance tuning does not require additional ALM resources … and
does not require additional changes or added complexity to the design's
place-and-route.”
The company reckons the design also
cuts down on on-chip routing congestion.
There's more on the architecture in
this white paper.
Oh, and it's got an on-chip ARM core.
Did we mention that? ®
